This ESC glossary defines the terms a fab engineer meets when specifying, operating, troubleshooting or sourcing an ESC for semiconductor wafer processing. Each entry is a short, precise definition. Together they cover the clamping physics, materials, construction, process context and service vocabulary used across the rest of this site. Use it as a quick reference alongside the detailed guides. Follow the links where a term has an article of its own.
To see how these terms fit together, read our complete guide to ESCs.
Clamping principles and electrical terms
| Term | Definition |
|---|---|
| ESC | A ceramic component that clamps a wafer and controls its temperature inside a vacuum process chamber. It uses an electrostatic field instead of vacuum or a mechanical ring. |
| Coulombic ESC | An ESC whose dielectric is a near-perfect insulator (above 10¹⁵ Ω·cm). Charge stays on the buried electrode. Release is fast, and force changes little with temperature. |
| Johnsen–Rahbek (JR) ESC | An ESC whose dielectric is slightly conductive (≈ 10¹⁰–10¹³ Ω·cm). Charge moves to the surface. This gives higher force per volt, with slower release and more temperature sensitivity. |
| Monopolar | An electrode design with a single electrode. It uses the surrounding plasma to complete its circuit, so it clamps only when plasma is present. |
| Bipolar | An electrode design with two opposite-polarity electrodes that close the circuit through the wafer. It clamps with or without plasma and keeps the wafer near ground potential. |
| Clamping force | The holding pressure the ESC exerts on the wafer, expressed in g/cm² or Torr-equivalent. A typical production ESC delivers 20–80 Torr-equivalent. |
| Chuck voltage | The high-voltage DC applied to the electrode to generate the clamp, typically 600–2,000 V DC. |
| Bulk resistivity | The electrical resistivity of the dielectric ceramic, measured in Ω·cm. Its value decides whether the ESC operates in the Coulombic or Johnsen–Rahbek regime. |
| Leakage current | The small current that flows through the dielectric under clamp voltage. A rising leakage current is an early sign of dielectric degradation. |
| Wafer bias | The RF or DC potential that develops on the wafer during processing. The ESC design must handle it without disturbing the clamp. |
| RF bias power | The radio-frequency power coupled to the wafer through the ESC to control ion energy at the surface. The dielectric and electrode must pass it without disturbing the DC clamp. |
| Sheath | The thin region of net positive charge between the plasma and the wafer surface. The bias voltage drops across it, and ions are accelerated through it into the wafer. |
| Dielectric breakdown | Failure of the dielectric when the field exceeds the material’s strength. It allows a conductive path from electrode to surface and destroys the clamp. It sets an absolute limit on usable chuck voltage. |
| Partial discharge / arcing | Localised electrical breakdown at a void, crack or contaminated point that does not yet bridge the full dielectric. Repeated arcing erodes the surface and comes before complete failure. |
| Hipot test | A high-potential test that applies a voltage above the working range. It confirms the dielectric withstands the voltage without breakdown or excessive leakage current. |
| Ground strap | The conductive connection that ties the ESC base or wafer return path to chamber ground. It gives the clamp circuit and RF return a defined low-impedance path. |
Materials and construction
| Term | Definition |
|---|---|
| Dielectric | The thin ceramic layer between the electrode and the wafer that insulates the electrode and sets the clamping regime. |
| Alumina (Al₂O₃) | A robust, cost-effective dielectric ceramic with high native resistivity, usually used for Coulombic ESCs. Doping lowers its resistivity into the JR band. |
| Aluminium nitride (AlN) | A dielectric ceramic with much higher thermal conductivity than alumina. It gives better wafer temperature uniformity and suits JR operation. |
| Doped ceramic | Alumina or a composite with additives such as titania. It is designed so the bulk resistivity falls precisely in the JR window. |
| Electrode | The conductive layer buried beneath the dielectric. The clamp voltage is applied to it. Monopolar designs have one electrode, bipolar designs have two. |
| Bond layer | The layer joining the ceramic puck to the cooled base plate. It must conduct heat and survive thermal cycling. |
| Base plate | The cooled metal body beneath the ceramic that carries the helium and coolant channels and sets the ESC temperature. |
| Mesa | One of the microscopic raised features on the clamping surface. Together they define the real wafer contact area and the volume available for backside helium. |
| Surface flatness | The flatness of the clamping surface, held to single-digit micrometres. This makes the wafer sit flat and contact evenly. |
| Coefficient of thermal expansion (CTE) | The rate at which a material expands with temperature. ESC layers are matched in CTE to survive repeated heating and cooling. |
| Lift pins | Retractable pins that raise the wafer off the ESC after dechuck so the handler can remove it. |
| Braze joint | A high-temperature metallurgical bond joining the ceramic puck to the metal base plate. It is used where a polymer bond layer cannot survive the thermal load. |
| Anodised coating | An aluminium-oxide layer grown electrochemically on the metal base plate to insulate and protect it from plasma and process chemistry. |
| Gas distribution holes | The small ports machined through the dielectric that feed backside helium evenly into the gap behind the wafer. |
| Outgassing | The slow release of adsorbed gas or moisture from ESC materials under vacuum. It can raise base pressure and add particles if the build is not vacuum-clean. |
| Vacuum compatibility | The requirement that every ESC material is low-outgassing and stable under high vacuum. This prevents contamination of the process chamber. |
| Wafer bow / warp | Out-of-plane curvature of the wafer. The clamp must flatten it against the ESC so the backside helium seals and the temperature stays uniform. |
Cooling, operation and release
| Term | Definition |
|---|---|
| Helium backside cooling | Feeding helium into the gap behind the clamped wafer (5–40 Torr) to conduct process heat to the cooled ESC body. |
| Backside pressure | The helium pressure behind the wafer. The clamping force must exceed it, or the wafer leaks or lifts. |
| Multi-zone control | Independent control of helium and base temperature across several radial zones to improve wafer temperature uniformity. |
| Thermal uniformity | How evenly the wafer temperature is held across its area. It directly affects process results such as etch rate and film properties. |
| Dechuck | The controlled sequence that releases the wafer after power-off, typically completing in under 1–5 s. |
| Residual clamping | Unwanted sticking caused by charge trapped in the dielectric after power-off. It is cleared with a reverse-polarity pulse and plasma-assisted discharge. |
| Reverse-polarity pulse | A brief opposite-polarity voltage applied during dechuck to neutralise trapped charge and release the wafer cleanly. |
| Helium leak rate | The rate at which backside helium escapes past the wafer seal. A rising leak rate indicates worn surface features or insufficient clamp force. |
| Clamp recipe | The programmed sequence of voltage ramp, settle time and helium turn-on. The tool runs it to engage the wafer at the start of a process step. |
| Dechuck recipe | The programmed release sequence that frees the wafer in under 1–5 s without sticking. It includes voltage removal, a reverse-polarity pulse and plasma-assisted discharge. |
| Cool-down step | A recipe step that holds the clamped wafer on the cooled ESC after processing. It lowers the wafer temperature before dechuck and transfer. |
| Edge ring / focus ring | A replaceable ring around the wafer. It shapes the plasma sheath to the wafer edge and protects the ESC periphery from erosion. |
| Thermal cycling | Repeated heating and cooling across process steps. It stresses the bond layer and CTE-matched interfaces, and in the end limits ESC life. |
Process context and service terms
| Term | Definition |
|---|---|
| Plasma etch | A process that removes material from the wafer using a reactive plasma. It is a demanding, high-heat application for the ESC. |
| PVD | Physical vapour deposition — depositing thin films by physical means such as sputtering. The ESC holds and cools the wafer. |
| CVD | Chemical vapour deposition — depositing films through chemical reaction of gases at the wafer surface. |
| Ion implantation | Driving dopant ions into the wafer. The ESC must manage charge and heat from the ion beam. |
| Wafer size | The wafer diameter the ESC supports: 100, 150, 200 or 300 mm. Much legacy capacity runs on 150 and 200 mm tools. |
| Defectivity / particle adders | Particles added to the wafer by the ESC or chamber. Low particle performance is a key ESC quality metric. |
| Erosion | Gradual loss of dielectric surface material under plasma exposure. It degrades clamping and particle performance over time. |
| OEM-equivalent | A direct-equivalent replacement ESC that fits and performs as the original-equipment part without being the OEM’s own product. |
| Refurbishment (L1 / L2) | Restoring a worn ESC to as-new condition, followed by a full functional test. L1 is a surface recondition. L2 is a full strip-to-frame rebuild. |
| Cost of ownership | The total lifetime cost of an ESC including purchase, repair and downtime. Refurbishment and OEM-equivalent supply both reduce it. |
| Conditioning / seasoning | Running a new or rebuilt ESC through controlled cycles before production. Its surface and clamping behaviour then settle to a repeatable baseline. |
| Particle excursion | A sudden rise in particle adders above the normal baseline. It often signals ESC surface wear or contamination, and it triggers investigation. |
| Mean time between failures (MTBF) | The average run time between ESC failures. It is used to plan preventive replacement or refurbishment before unplanned downtime occurs. |
| Functional test | The bench verification of clamp voltage, clamping force, helium leak rate and particle performance. It confirms a repaired or replacement ESC meets specification before return. |
When an ESC reaches the end of its service life, several terms above describe the warning signs: erosion, rising leakage current, residual clamping and helium leak rate. These signs point to the options covered in ESC repair and refurbishment.
Frequently asked questions
What is the difference between clamping force and backside pressure?
Clamping force is the electrostatic pressure that holds the wafer down (20–80 Torr-equivalent). Backside pressure is the helium pressure that pushes it up for cooling (5–40 Torr). The clamping force must always be higher than the backside pressure.
What units is ESC clamping force given in?
Most often as a pressure, in g/cm² or Torr-equivalent. In production, the key question is whether the ESC can hold the wafer against the helium backside pressure.
What do L1 and L2 mean in ESC repair?
L1 is a surface recondition that restores the clamping surface. L2 is a full strip-to-frame rebuild. Both finish with a full functional test to confirm clamping and particle performance.